Conventional integrated circuit fabrication techniques have utilized multi-chip semiconductor substrates to increase integration density of electronic circuits within packaged integrated circuit devices. In addition to increasing integration density, multi-chip semiconductor substrates may improve device performance by reducing signal line delays and other parasitics associated with chip-to-chip electrical interconnects when mounted in a single integrated circuit package. Conventional techniques to form multi-chip substrates frequently include bonding multiple semiconductor chips together to form a substrate stack. For example, one conventional multi-chip fabrication technique is disclosed in U.S. Pat. No. 6,667,225 to Hau-Riege et al., entitled “Wafer-Bonding Using Solder and Method of Making the Same.” The '225 patent discloses forming a two-wafer stack by solder bonding a first plurality of metallized trenches within a first wafer to a second plurality of metallized trenches within a second wafer. Another multi-chip fabrication technique, which is disclosed in U.S. Pat. No. 6,586,831 to Gooch et al., entitled “Vacuum Package Fabrication of Integrated Circuit Components,” describes mating a device wafer to a lid wafer using aligned sealing rings on both wafers and then dicing the joined wafers into individual dies.
Conventional multi-chip fabrication techniques may also utilize electrically conductive “through-substrate” connection vias to support chip-to-chip bonding. Such techniques are disclosed in U.S. Pat. No. 7,276,799 to Lee et al., entitled “Chip Stack Package and Manufacturing Method Thereof.” Related multi-chip fabrication techniques are also disclosed in U.S. Pat. Nos. 6,607,938 and 6,566,232.